(1) Field of the Invention
This invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device formed on an SOI (silicon-oninsulator) substrate and a method for fabricating the same.
(2) Description of the Related Art
To assist the understanding of the invention, the prior art is first described with reference to FIGS. 1 to 4. FIG. 1 is a sectional view showing "inter-element isolation by a selective oxidization process" in the prior art, and FIG. 2 is a sectional view showing "inter-element isolation by a trench isolation process" in the prior art.
FIG. 3 is a sectional view for showing the formation of element isolation using an SOI substrate in a prior art example, and FIG. 4 is a sectional view for showing a semiconductor chip with a combination of a deep trench for inter-element isolation and a shallow trench for minimizing substrate-related capacitances (i.e., capacitances to the substrate) in a prior art example.
In FIGS. 1 to 4, like parts are designated by like reference numerals and symbols, designated at 1 is a silicon substrate, at 2 a silicon oxide film, at 3 a single crystal silicon layer, at 3a an n.sup.+ -buried layer, at 3c an emitter region, at 3d a base region, at 3e a collector region, and at 8 and 8a a silicon oxide film. Designated at 5 is an element region, and at 6 a non-element region.
Heretofore, in a bipolar type semiconductor integrated circuit using a silicon substrate, the inter-element isolation is made using the selective oxidization process as illustrated in FIG. 1 or the trench separation process as illustrated in FIG. 2.
In the selective oxidization process, the inter-element isolation is made by selectively forming a silicon oxide film 8 using a patterned silicon nitride film or the like as a mask (see FIG. 1). In the trench isolation process, the inter-element isolation is made by forming a trench around each element by silicon etching and filling the trench with polycrystalline silicon or an insulator, e.g., silicon oxide film 8a (See FIG. 2).
Recently, high quality SOI substrates based on a SIMOX (separation by implanted oxygen) process and a wafer-bonding process have become available, and thus it has become possible to isolate completely an element region 5 with an insulator as shown in FIG. 3 by forming a trench in the surface of a non-element region 6 of a single crystal silicon layer 3 which is formed on a silicon substrate 1 via a silicon oxide film 2 such that the trench reaches the silicon oxide film 2 and filling the trench with a silicon oxide film 8a.
In the structure shown in FIG. 3, the single crystal silicon layer in the element region 5 is completely enclosed by the insulator. Thus, with this structure, compared to the usual selective oxidization isolation structure (see FIG. 1) or the trench isolation structure (see FIG. 2) using a silicon substrate, the reliability of insulator isolation is improved. In addition, there is the following advantage.
Where the SOI structure shown in FIG. 3 is utilized, the junction capacitances corresponding to those present between n-type collector region 3e and the p-type silicon substrate 1 in the selective oxidization process in FIG. 1 or the trench isolation process in FIG. 2, are insulating film capacitances of the silicon oxide film 2 (see FIG. 3). Where the thickness of the silicon oxide film 2 exceeds about 0.2 .mu.m, the capacitances are low compared to the junction capacitances noted above. This is advantageous for the operation speed increase of element.
The element isolation using such SOI substrate, is basically the same as the usual trench isolation process using a silicon substrate (see FIG. 2). In this case, the trench is formed selectively in the single crystal silicon layer 3 from the surface of a non-element region by using the ordinary photolithographic technique (see FIG. 3).
In this technique, the etching is silicon etching based on a dry etching process, and the trench as shown in FIG. 3 can be easily formed by suitably selecting a condition of satisfactory selectivity with respect to the silicon oxide film.
Further, the burying of the insulator in the trench is possible as in the usual trench isolation process using a silicon substrate, and a perfect insulator isolation structure is obtainable without a substantial process change.
In the structure shown in FIG. 3, the non-element region 6 is constituted by the same single crystal silicon layer 3 as in the element region 5. The single crystal silicon layer 3 is usually an impurity-doped conductor. Therefore, where interconnects or wiring are formed on this layer via an insulator, wiring-substrate capacitances are high compared to the case where the thick silicon oxide film 8 formed by the selective oxidization process as shown in FIG. 1 is present.
Accordingly, in the prior art structure as shown in FIG. 3, there is provided with selective oxidization as shown in FIG. 1. Alternatively, as shown in FIG. 4, a deep trench for isolating inter-elements and a shallow trench for reducing the substrate-related capacitances.
With such structures, it is possible to reduce wiring-substrate capacitances to certain extents and improve the switching speed of a semiconductor integrated circuit.
The structure as shown in FIG. 4 has been reported under the title "FULLY SiO.sub.2 HIGH SPEED SELF-ALIGNED BIPOLAR TRANSISTOR ON THIN SOI" by H. Nishizawa et al. in "Symposium on VLSI Technology Digest", 1991, pp. 51-52.
In the prior art example shown in FIG. 4, in the shallow trench part of the non-element region 6, the single crystal silicon layer 3 still remains under the shallow trench and over the silicon oxide film 2. Thus, the wiring-substrate capacitances are insulating film capacitances of the silicon oxide film 8a in the shallow trench and the silicon oxide film 2.
In view of the speed increase of the semiconductor integrated circuit, the non-element region 6 is suitably a thicker insulating film. However, if it is intended to increase the thickness by the selective oxidization process as shown in FIG. 1, it will result in a high stress generated on the element region. Such a structure is inadequate.
Further, the structure as shown in FIG. 4 is required to form the deep and shallow trenches separately, thus increasing the number of fabrication steps for the element isolation.
FIG. 5 is a sectional view showing a first semiconductor device according to the invention to be described later in detail. The Figure is for describing the dissipation of heat generated in the element region.
In this case, as shown in FIG. 5, the silicon oxide film 8 or like insulator may bury the entire non-element region 6 other than the element region 5 on the silicon oxide film 2. With this structure, it is possible to make a large reduction in the wiring-substrate capacitances.
However, the structure shown in FIG. 5 has a drawback that the dissipation of heat generated in the element region 5 and heat generated in the wiring and resistive element parts in the non-element region 6 is inferior.
Specifically, the thermal conductivity of silicon is about 170 Wm.sup.-1 K.sup.-1, while the thermal conductivity of the silicon oxide film is about 1/100 of this value. Therefore, since heat generated in the semiconductor integrated circuit is not efficiently dissipated to the silicon substrate, such semiconductor integrated circuit is not suitable to be used in the application where power consumption is large.
FIG. 6 is a view for describing the "recession" which is formed in a flattening process by way of polishing the silicon oxide film.
The recession will be described later in detail. To flatten the silicon oxide film 8 by polishing, it is necessary to make slight over-polishing by taking fluctuations of the polishing speed in the surface of the silicon substrate 1 into considerations. Therefore, the recession 15 as shown in FIG. 6, although varied in dependence on the method and conditions of polishing, is formed in the non-element region 6, thus making it difficult to make a completely flattened or uniform surface.